1. Field of the Invention
The present invention relates to a miniature inductor suitable for integrated circuits, and in particular to a miniature inductor having a folded coplanar strip line.
2. Description of the Related Art
In the prior art, a miniature inductor for integrated circuits occupies a quite large area, and is easily affected by material loss, and has low quality factor and low self-resonant frequency.
Currently, there are various ways to manufacture an inductor in general integrated circuit manufacturing process technology. For example, U.S. Pat. No. 6,714,113, entitled “Inductor for Integrated Circuits”, filed in April, 2004 by W. Abadeer et al., and Paper “Microwave Inductors and Capacitors in Standard Multilevel Interconnect Silicon Technology,” IEEEMTT, January 1996, submitted by J. N. Burghartz et al. all use a microstrip line structure, which is planar. Although it adopts a spiral line shape or a folded line shape, the disadvantage is that it takes up a larger area. Moreover, in integrated circuit silicon manufacturing process, an inductor is easily affected by substrate loss, and it is difficult to enhance quality factor.
Furthermore, in accordance with paper “Miniature 3D Inductors in Standard CMOS Process” submitted in April, 2002 by C.-C. Tang et al., an inductor is designed into a 3D type by using a multilevel metal interconnection structure, such that its occupied area can be reduced. The disadvantage is that the multilevel structure causes a larger parasitic capacitance, resulting in lower frequency bandwidth (it is difficult to be increased to more than 10 GHz). Moreover, in paper “Differentially Driven Symmetric Microstrip Inductors” submitted in January, 2002 by Danesh et al., it is discussed that if a microstrip line is used differentially, quality factor can be greatly increased. However, the disadvantage is that it cannot reduce the occupied area.